| 1 | Low Power and Area Efficient Shift Register Using Pulsed Latches |
| 2 | Scan Test Bandwidth Management for Ultra Large-Scale System-on-Chip Architectures |
| 3 | Fault Tolerant Parallel Filters Based on Error Correction Codes |
| 4 | Low Complexity Tree Architecture for Finding the First Two Minima |
| 5 | Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder |
| 6 | VLSI Computational Architectures for the Arithmetic Cosine Transform |
| 7 | Aging Aware Reliable Multiplier Design with Adaptive Hold Logic |
| 8 | Fully Reused VLSI Architecture of FM0 / Manchester Encoding Using SOLS Technique for DSRC Applications |
| 9 | A Novel Fault Detection and Correction Technique for Memory Applications |
| 10 | An Efficient Binary Multiplier Design for High Speed Applications Using Karatsuba and Urdhva Tiryagbhyam Algorithms |
| 11 | Flexible DSP Accelerator Architecture Exploiting Carry Save Arithmetic |
| 12 | A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT |
| 13 | Optimized Designs of Reversible Fault Tolerant BCD Adder and Reversible Carry Skip BCD Adder |
| 14 | A Modified Partial Product Generator for Redundant Binary Multiplier |
| 15 | OCNOC: Efficient One Cycle Router Implementation for 3D Mesh Network-on-Chip |
| 16 | FPGA Implementation of an Efficient Vedic Multiplier |
| 17 | An Optimized Modified Booth Recoder for Efficient Design of Add-Multiply Operator |
| 18 | Fault Tolerant Parallel FFT Architectures Using Error Correction Codes and Parseval Checks |
| 19 | Multifunction Residue Number System Architectures for Cryptography |
| 20 | An Efficient Design of 16-Bit MAC Unit Using Vedic Mathematics |
| 21 | A Further Optimized Mix Column Architecture Design for the Advanced Encryption Standard (AES) |
